The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction (the current flow direction).
Worldwide researches are actively being undertaken in the area of nano-CMOS device technologies since the applications of nano-CMOS technologies in logic circuits and memories have the capability of creating substantial value added revenues.
The system based on the silicon semiconductor technology is becoming smaller and requires low electric power consumption. The size of its devices should be small accordingly.
The most competitive device technology which can meet those requirements is the CMOS device technology.
The gate size of these devices is presently being scaled down, however, some problems are occurring with the scaling-down.
The biggest problem is so called short channel effects. The conventional CMOS devices have mainly fabricated using bulk silicon substrates. The MOS device fabricated on a bulk silicon substrate has device characteristics which are sensitively affected by the fabrication conditions as the length of a gate is being scaled down to a size of less than 50 nm. Also, the device performance of CMOS devices with the channel length around 30 nm is insufficient to be implemented in a real circuit.
A 30 nm CMOS device which is developed by Intel has poor I-V characteristics by considering scaling-down trend of the conventional devices.
There are only small margins for improving the integration density by reducing the actual area occupied by a single device since the spacer region formed at the both sides of a gate has not been scaled down.
Due to the limitation of MOS device technology based on bulk silicon substrates, active researches have been focused on realizing a device with the channel length below 30 nm using Silicon On Insulator (SOI) substrates.
Many research results have been published on analyzing the characteristics of the conventional device structures on a SOI substrate rather than on a bulk substrate, however, the parasitic resistance of the source/drain region due to thin film thickness becomes too large and consequently requires a selective growth of an epitaxial layer in the source/drain region.
Also, the SOI devices, in which the body of a device is not connected to a substrate, have resulted floating body effects and low heat transfer rates, and consequently causing the deterioration in the device performance.
As explained above, the scaling-down characteristic of the conventional device structure implemented on a SOI substrate is not much improved by comparing that of device implanted on a bulk substrate.
A double-gate device structure has emerged as the most appropriate device structure for reducing the channel length of a CMOS device below 25 nm or less.
A double-gate device comprises gate electrodes at the top/bottom or left/right of a channel where the current flows, shows a significant improvement in gate control characteristics of the channel through gate electrodes.
In case where the channel is controlled well by gate bias, the leakage current between a source and a drain can be improved, which leads to the lower Drain Induced Barrier Lowering (DIBL) effect.
Also, due to the presence of gates at the both sides of a channel region, the threshold voltage of the device can be dynamically changed, resulting in much improved on-off channel characteristic in comparison to the conventional single-gate structures and successfully suppressing the short channel effects.
FIG. 1 shows a brief representation of the directions of the current flow in the channel of a double-gate structure formed on the surface of a wafer having a crystal orientation of (100).
A gate 32 is formed at the top/bottom or left/right of a body (channel 34).
FIG. 1a shows a kind of three-dimensional device in which the source/drain region is formed at the top/bottom and the current flows from top to bottom (or vice versa) and a channel 34 is formed at right angles to a (100) wafer.
FIG. 1b shows a standard double-gate MOS device structure in which a channel 34 is formed on the same surface of a (100) wafer and gates 32 are formed at the top and bottom of the channel 34 and the current flows on the surface direction of 100 crystallographic orientation.
FIG. 1c shows a channel 34 which is formed at right angles to the surface of a (100) wafer, and the source/drain region is not formed at the top/bottom of the channel as shown in FIG. 1a. The current flows on both surfaces of the channel (or fin) 34 formed at right angles to the surface of a (100) wafer.
FIG. 2 shows the essential parts of a conventional FinFET structure where the metal layer for wiring was omitted for simplicity.
FIG. 2a and FIG. 2b represent the same structures where FIG. 2a is semi-transparent and FIG. 2b is shaded. Here, the structure and the current flow direction correspond to those of FIG. 1c. The short channel effects can significantly be reduced by forming a gate electrode 16 at both (top/bottom) sides of the channel 34. A silicon substrate 2a of SOI wafer, oxide layers 6, 10 and a gate oxide layer 12 are shown in FIG. 2a. 
Hereinafter, the methods of fabricating a double-gate device with the same characteristics as shown in FIG. 1b and FIG. 1c will be described.
First, the key features shown in FIG. 1b will be explained. In FIG. 1b, the current flows to the same horizontal direction as the surface of a (100) wafer. In this structure, the channel 34 is formed on the surface of a (100) wafer like the conventional MOSFETs. Hence, the surface characteristic of Si—SiO2 is not inferior to that of the conventional MOSFETs.
In a double-gate device as shown in FIG. 1b, gates 32 are formed at the top/bottom of a channel 34.
This device structure enables a thin and uniform control of Si film thickness in a silicon body region.
In order to form gates 32 at the top/bottom of a channel 34, wafer bonding process and etch-back process have to be performed by utilizing Micro Electro-Mechanical System (MEMS) technology which makes the fabricating process very complicated.
One of the most important requirements for the double-gate MOS device is that two gates 32 must be self-aligned, otherwise, the device characteristics deteriorate significantly.
A considerable effort has been concentrated on forming a self-aligned gates 32 for the device as shown in FIG. 1b where gates are formed at the top/bottom of a channel 34. Many complications have arisen from the material and complexity of the fabrication process.
In order to improve the scale-down characteristics of the device, the channel silicon film thickness should be reduced to 20 nm or less.
If the silicon film with a thickness of 20 nm or less is used for the channel and source/drain region, the short channel effects could be improved, however, the device characteristics would deteriorate due to a significant increase in source/drain parasitic resistance.
In order to realize both self-alignment and reduction in the source/drain resistance, the complexities of fabrication process should be accepted as a consequence.
Second, the other method of implementing a double-gate MOS device includes forming the gate 32 on both sides of the channel 34 as shown in FIG. 1c is described.
The MOS device in FIG. 1c is called FinFET. In the double-gate device as shown in FIG. 1c, the width of the channel region 34 is patterned to be in a nano-meter size (50 nm or less). The double-gate device uses the etched vertical surfaces on both sidewalls of the body as the main channel regions.
In the above structure, the channel 34 is formed at right angles to the wafer surface.
The fabrication method as shown above has a more simplified fabrication process in comparison to the structure (FIG. 1b) which has gates 32 at the top/bottom.
However, since the channel 34 is formed on the side of the film which is formed at right angle to the surface of a (100) silicon wafer, the crystallographic orientation of the channel becomes 110 and the surface characteristics of the orientation 110 is inferior to that of the conventional 100 surface.
In order to resolve this problem, the body which includes the channel region is formed at 45 degree to the primary flat zone of (100) wafer to form a channel on (100) silicon surface of the body.
The silicon region of the channel is defined by nano-patterning technology. Hence, the device characteristics with the pattern size variation could be relatively large since the variation in size control of the body is larger than that of the double-gate device shown in FIG. 1b where a gate is formed at the top/bottom. Basically, FIG. 1b structure has self-aligned gates which are formed at both sides of the channel 34.
However, the source/drain region formed in thin body region has the same nano-size body width as the channel region and it reduces the current drive capability due to an increase in the source/drain parasitic resistance.
In order to resolve this problem, it was tried to deposit polycrystalline silicon or SiGe layer on the source/drain region as a non-self-aligned manner. However, their impact was not significant since the parasitic resistance between the thin width channel and source/drain region was not reduced in spite of the new fabrication methods that were either being added or altered.
Thus, a double-gate MOS device formed on a conventional SOI silicon substrate is more expensive than that on a bulk wafer. It also has a larger the source/drain parasitic resistance.
Like a floating body SOI devices, the body 34 where a channel is formed as shown in FIG. 2 is not connected to the SOI silicon substrate 2a, hence, the floating body problem may be arisen. Also, since an oxide film 10 on a SOI silicon substrate 2a which is blocking the heat, which is generated by the device, being transferred to the SOI silicon substrate 2a, the device characteristic deteriorates.